As device densities continually increase on a semiconductor wafer, device dimensions are further scaled down to smaller feature size. With such smaller feature size, higher resolution photolithographic processes are desired. In general, lithography refers to processes for pattern transfer between various media. As known to one of ordinary skill in the art of integrated circuit fabrication, exposure of a photoresist layer on a semiconductor wafer to a pattern of illumination (such as from ultraviolet light, x-rays, or an electron beam) results in a desired pattern on the semiconductor wafer for further processing.
For smaller feature size, projection lithography and use of extreme violet (EUV) radiation are important tools for integrated circuit fabrication. Extreme ultraviolet (EUV) radiation has a wavelength range of about 50 to 700 .ANG. (Angstroms) (i.e, about 5 to 70 nm (nanometer)). A projection lithography system 100 using EUV radiation is illustrated in FIG. 1. In the projection lithography system 100, an EUV light source 102 provides EUV radiation as known to one of ordinary skill in the art.
An EUV mask 104 has a pattern of regions which absorb the EUV radiation from the EUV light source 102 and regions which reflect the EUV radiation from the EUV light source 102 to produce a reflected image. A reflective imaging system 106 (which is typically comprised of a series of high precision mirrors) projects the reflected image by de-magnifying or reducing the reflected image from the EUV mask 104 onto a semiconductor wafer 108. The semiconductor wafer 108 has a photoresist layer that is patterned to the de-magnified reflected image from the reflective imaging system 106.
The EUV mask 104 is a reflective reticle having a pattern comprised of regions which absorb the EUV radiation from the EUV light source 102 and regions which reflect the EUV radiation from the EUV light source 102. The regions which absorb the EUV radiation and the regions which reflect the EUV radiation are formed as shown in FIG. 2. Referring to FIG. 2A, a reflective layer 202 is formed on a substrate layer 204 of silicon or glass. The reflective layer 202 is typically a multilayer coating of alternating layers of molybdenum and silicon having respective thickness of approximately 40 .ANG. (angstroms). The reflective layer 202 is designed to reflect the EUV radiation with high efficiency (e.g., about 65% or more).
The reflective layer 202 is then covered with a buffer layer 206 to protect the reflective layer 202 and to prevent oxidation of the reflective layer 202 during subsequent processing of the EUV mask. The buffer layer 206 may be comprised of one of silicon dioxide or silicon nitride. An absorber layer 208 is deposited on top of the buffer layer 206, and the absorber layer is comprised of EUV absorptive material such as silver, tungsten, gold, tantalum, titanium, lead, polyimide, polymethyl methacrylate, etc.
Referring to FIG. 2B, the desired pattern for the regions which absorb the EUV radiation is made by a patterned photoresist layer 210 as known to one of ordinary skill in the art. Referring to FIG. 2C, the absorber layer 208 is patterned according to the photoresist layer 210. Referring to FIG. 2D, the photoresist layer 210 is then removed. The buffer layer 206 protects the reflective layer 202 during the etching of the absorber layer 208 and the removal of the photoresist layer 210.
Referring to FIG. 2E, the buffer layer 206 is selectively removed for exposing the reflective layer 202 in regions without the absorptive material of the absorber layer 208. In this manner, a pattern of regions that absorb the EUV radiation is formed where the absorptive material of the absorber layer 208 remain. The regions where the reflective layer 202 is exposed reflect the EUV radiation. Referring to FIG. 2F, a capping layer 212 of amorphous silicon of approximately 70 .ANG. (Angstroms) may also be deposited on top of the reflective layer 202 to protect the reflective layer 202.
During fabrication of the EUV mask 104 as shown in FIGS. 2A, the buffer layer 206 is deposited on top of the reflective layer 202. The reflective layer 202 is a delicate structure of thin layers (having respective thicknesses of approximately 40 .ANG. (Angstroms)) of alternating molybdenum and silicon. To fabricate an effective EUV mask 104, a process is desired for depositing the buffer layer 206 on top of the reflective layer 202 which also preserves the integrity of the reflective layer 202.
The buffer layer 206 is typically comprised of one of silicon dioxide or silicon nitride. In the prior art, processes for depositing silicon dioxide or silicon nitride typically use high temperatures of around 300.degree. C. to 400.degree. C. However, such high temperatures may degrade the structure of the reflective layer 202 which is comprised of thin alternating layers of molybdenum and silicon. A process for depositing silicon dioxide using lower temperatures of approximately 170.degree. C. or less is described in copending patent application with Ser. No. 09/212,198 filed on Dec. 15, 1998 and having common inventors and assignee herewith. In addition, a process for depositing silicon nitride using lower temperature of approximately 170.degree. C. or less is desired for depositing the buffer layer 206 such that the structural integrity of the reflective layer 202 is preserved when silicon nitride is used for the buffer layer 206.